NAME

       libpfm_intel_nhm - support for Intel Nehalem core PMU

SYNOPSIS

       #include <perfmon/pfmlib.h>

       PMU name: nhm
       PMU desc: Intel Nehalem
       PMU name: nhm_ex
       PMU desc: Intel Nehalem EX

DESCRIPTION

       The  library  supports the Intel Nehalem core PMU. It should be noted that this PMU model only covers the
       each core's PMU and not the socket level PMU. It is provided separately.  Support  is  provided  for  the
       Intel Core i7 and Core i5 processors.

MODIFIERS

       The following modifiers are supported on Intel Nehalem processors:

       u      Measure at user level which includes privilege levels 1, 2, 3. This corresponds to PFM_PLM3.  This
              is a boolean modifier.

       k      Measure at kernel level which includes privilege level 0. This corresponds to PFM_PLM0.  This is a
              boolean modifier.

       i      Invert  the  meaning  of  the  event.  The counter will now count cycles in which the event is not
              occurring. This is a boolean modifier

       e      Enable edge detection, i.e., count only when there is a state transition from no occurrence of the
              event to at least one occurrence. This modifier must be combined with a counter mask modifier  (m)
              with a value greater or equal to one.  This is a boolean modifier.

       c      Set  the  counter  mask  value. The mask acts as a threshold. The counter will count the number of
              cycles in which the number of occurrences of the event is greater or equal to the threshold.  This
              is an integer modifier with values in the range [0:255].

       t      Measure  on  both  threads at the same time assuming hyper-threading is enabled. This is a boolean
              modifier.

       ldlat  Pass a latency threshold  to  the  MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD  event.   This  is  an
              integer  attribute  that must be in the range [1:65535]. It is required for this event.  Note that
              the event must be used with precise sampling (PEBS).

OFFCORE_RESPONSE event

       The library is able to encode the OFFCORE_RESPONSE_0 event. This is a special event because  it  needs  a
       second  MSR  (0x1a6) to be programmed for the event to count properly. Thus two values are necessary. The
       first value can be programmed on any of the generic counters. The second value goes  into  the  dedicated
       MSR (0x1a6).

       The  OFFCORE_RESPONSE  event  is  exposed  as a normal event with several umasks which are divided in two
       groups: request and response. The user must provide at least one umask from each  group.   For  instance,
       OFFCORE_RESPONSE_0:ANY_DATA:LOCAL_DRAM.

       When  using pfm_get_event_encoding(), two 64-bit values are returned. The first value corresponds to what
       needs to be programmed into any of the generic counters. The second value must  be  programmed  into  the
       dedicated MSR (0x1a6).

       When  using  an  OS-specific  encoding routine, the way the event is encoded is OS specific. Refer to the
       corresponding man page for more information.

AUTHORS

       Stephane Eranian <eranian@gmail.com>

                                                 September, 2009                                       LIBPFM(3)